Case Study 1 : LVDS Rx Electrical PHY for 4K2K Resolution Displays

    Brief Description of the Project requirement:

    Our customer wanted us to study the feasibility, develop the suitable architecture and perform the design of a high speed Receiver Electrical PHY with data rate of close to 52.8Gbps for use in 3D and 4K2K resolution Projector Drivers and Flat Panel Displays.


    The customer was targeting this chip to be designed within a power consumption specification of 1W. ELVEEGO was required to also analyse the feasibility of this design and make architecture level suggestions and decisions like number of channels, data rate per each channel, requirement of CDR circuit and how many data channels can be supplied by one CDR etc., Various failsafe and Test mode options were also to be included to enable testing of each block individually as part of the design policy for Test (DFT).

    Solutions and Project Execution Summary:

    The feasibility study of this project was performed using various Verilog-A models of each sub-blocks like CDR, Sampler, PLL, LVDS receiver etc., along with parasitics models considering the number of channels (in this case 44 channels) and their placements. Based on the feasibility study, the suitable system architecture was established. Also based on the system timing budget, timing specifications for all sub-blocks were derived. In this chip, 44 data channels with 1.2Gbps data rate per channel are deserialized to (44X6) parallel data lines and provided to the digital core.

    The operating conditions and specifications of sub-blocks like operating frequency, voltage range specs etc., were decided considering the target Power consumption spec of less than 1W for the complete 44 channel Electrical PHY. The LVDS Interface section was designed at 3.3V typical Power Supply and the other sections like PLL, CDR, Sampler, Control and Deserializer etc., were designed using 1.2V typical Power Supply.

    This design was performed on Fujitsu 130nm CMOS process and was executed within a time frame of around 6 months from Specifications through GDS delivery.

    Present Status

    The design of the chip has been successfully delivered to the end customer for integration into 44 channels.