Case Study 6 : Low Noise Amplifier for short range communications receiver

    Brief Description of the Project requirement:

    The customer wanted Elveego to develop suitable architecture and make design up to GDSII of a low noise amplifier which is to be used in short range Wireless communications receiver. The target application was in the receiver front end of a medical diagnostic equipment. The frequencies of communication were less than 50MHz and very low noise requirement was a key feature of this amplifier.


    The customer was targeting this chip for usage in a highly noisy environment and the diagnostic equipment was also required to operate with strong interfering signals in similar frequency range. The gain tolerance specifications were tight with permitted gain variations not exceeding +/-0.2dB. The input referred noise of the LNA was required to be less than 1nV/sqrt(Hz), with input impedance matching required in the range of a few hundreds of Ohms. Offset requirements of less than +/- 1mV under 3-sigma conditions were also part of the specifications. Usage of a CMOS process was the requirement at a time when many commercial circuits of similar specifications were made with Bipolar technology.

    Solutions and Project Execution Summary:

    Elveego has studied various architectures for usage in the target LNA and had come up with a design which satisfies the given noise and offset requirements. The design was made using TSMC 0.18um CMOS process, with 3.3V typical supply voltage. The noise and offset specifications were simulated and verified extensively using statistical simulations. However the design translated to have a huge input capacitance. The stability problems because of the large input capacitance were mitigated using a split compensation scheme in a feedback loop, which also stabilized the gain to achieve the target gain variation range of less than +/-0.2dB. The design also had a buffer with programmable gain at the output which produced an output differential swing of hundreds of mV and was driving a large off-chip capacitance.

    The project execution duration was 3 months from specifications and concept up to GDSII delivery.

    Present Status

    The design was successfully taped out and is part of a chip under commercial mass production.