Case Study 5 : Direct Sampling RF Front End ADC design

Brief Description of the Project requirement:

The customer wanted ELVEEGO to investigate an existing design of RF Front End and redesign a Pipelined ADC used for Direct Sampling of RF signal at L1, L2 and L5 RF bands. The scope of work included the design of sub-sampling Pipelined ADC, Capacitor Array DAC, impedance matching Network for interfacing AGC output to the ADC input, LVDS Receiver Block for receiving Clock for the ADC, LVDS Transmitter Block for transmitting the ADC outputs and integration of these blocks. Also, the ADC had Cancellation techniques for Offset and mismatch in the Digital Error Correction block.

Challenges:

This project involved sub-sampling technique in which RF signal at around 1.6GHz frequency is directly sampled using a 100MHz sampling clock in the ADC. Also, the customer had a very tight schedule of less than 3 months to perform the complete design of this project.

Solutions and Project Execution Summary:

ELVEEGO took up the task of designing the Pipelined ADC, LVDS transmitter and Receiver Blocks and Integration of these blocks along with the Impedance matching network. The design of the Capacitor Array DAC which sets the gain of the AGC block of the RFFE was also designed by the same team. The design of the first stage of the ADC like Sample and Hold Amplifier etc., was challenging as RF signal was directly received by these blocks. Lots of design care and techniques were used to address Clock feed through and Switch leakage issues etc.,

This project was completed within a time frame of 3 months for the redesign, layout and GDS delivery.

Present Status

The design was successfully delivered to the customer and the customer has successfully tested the RFFE chip which is found to be working successfully even after Burn-In test for Space applications.