Case Study 2 : LVDS SerDes Electrical PHY for High resolution FPDs

    Brief Description of the Project requirement:

    The customer wanted ELVEEGO to design LVDS data and clock channel links section of a Baseband chip for millimetre wave Wireless communication system. The project scope included design of LVDS Transmitter and Receiver Buffers for data and clock and related Bias blocks; and then integration of the buffers as part of the I/O section of the Baseband Chip. In this channel design, there were 11 transmitter channels and 11 receiver channels. The data rate requirement for the transmitter buffer was 1.152Gbps per channel and data rate for the receiver buffer was 864Mbps per channel.


    The main challenge in this project was very low power consumption and low voltage operation requirements. Also, modelling of the layout parasitics for 11 Transmitter channels and 11 Receiver channels were to be done during the design and modelled along with the package and transmission medium models to account for the actual channel to channel, Package and transmission medium influence on the overall performance of the link.

    Solutions and Project Execution Summary:

    This Channel link was designed on TSMC 40nm process with 2.5V as the typical I/O power supply and 1.1V as the typical core power supply. The design was achieved with a maximum current consumption of 4.6mA for one transmitter buffer channel (3.5mA Drive current) with random data pattern at 1.152Gbps data rate per channel and with a current consumption of 1.51mA for one receiver buffer channel with random data pattern at 864Mbps data rate per channel. Options to program and select desired LVDS swing level was provided in the transmitter buffer.

    ELVEEGO has designed the schematic, layout of the individual buffers and then integrated those into the channel link with 11 transmitter and 11 receiver buffers along with their related Bias blocks. Integrated simulations were performed at schematic and post-layout levels and finally the GDS of this integrated channel link was delivered to the customer.

    This project was executed within a time frame of around 3 months for the design from Specification through GDS delivery under the turnkey design service model.

    Present Status

    The design has been successfully proven on silicon and as per the end customer’s press release then, this design is part of a world’s fastest millimetre Wave Wireless communication system with data transmission at 6.3Gbps which is achieved with very low power consumption.